
/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 14.6 EDK_P.68d
* DO NOT EDIT.
*
* Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

* 
* Description: Driver configuration
*
*******************************************************************/

#include "xparameters.h"
#include "xbram.h"

/*
* The configuration table for devices
*/

XBram_Config XBram_ConfigTable[] =
{
	{
		XPAR_MICROBLAZE_0_D_BRAM_CTRL_DEVICE_ID,
		XPAR_MICROBLAZE_0_D_BRAM_CTRL_DATA_WIDTH,
		XPAR_MICROBLAZE_0_D_BRAM_CTRL_ECC,
		XPAR_MICROBLAZE_0_D_BRAM_CTRL_FAULT_INJECT,
		XPAR_MICROBLAZE_0_D_BRAM_CTRL_CE_FAILING_REGISTERS,
		XPAR_MICROBLAZE_0_D_BRAM_CTRL_CE_FAILING_REGISTERS,
		XPAR_MICROBLAZE_0_D_BRAM_CTRL_UE_FAILING_REGISTERS,
		XPAR_MICROBLAZE_0_D_BRAM_CTRL_UE_FAILING_REGISTERS,
		XPAR_MICROBLAZE_0_D_BRAM_CTRL_ECC_STATUS_REGISTERS,
		XPAR_MICROBLAZE_0_D_BRAM_CTRL_CE_COUNTER_WIDTH,
		XPAR_MICROBLAZE_0_D_BRAM_CTRL_ECC_ONOFF_REGISTER,
		XPAR_MICROBLAZE_0_D_BRAM_CTRL_ECC_ONOFF_RESET_VALUE,
		XPAR_MICROBLAZE_0_D_BRAM_CTRL_WRITE_ACCESS,
		XPAR_MICROBLAZE_0_D_BRAM_CTRL_BASEADDR,
		XPAR_MICROBLAZE_0_D_BRAM_CTRL_HIGHADDR,
		XPAR_MICROBLAZE_0_D_BRAM_CTRL_S_AXI_CTRL_BASEADDR,
		XPAR_MICROBLAZE_0_D_BRAM_CTRL_S_AXI_CTRL_HIGHADDR
	},
	{
		XPAR_MICROBLAZE_0_I_BRAM_CTRL_DEVICE_ID,
		XPAR_MICROBLAZE_0_I_BRAM_CTRL_DATA_WIDTH,
		XPAR_MICROBLAZE_0_I_BRAM_CTRL_ECC,
		XPAR_MICROBLAZE_0_I_BRAM_CTRL_FAULT_INJECT,
		XPAR_MICROBLAZE_0_I_BRAM_CTRL_CE_FAILING_REGISTERS,
		XPAR_MICROBLAZE_0_I_BRAM_CTRL_CE_FAILING_REGISTERS,
		XPAR_MICROBLAZE_0_I_BRAM_CTRL_UE_FAILING_REGISTERS,
		XPAR_MICROBLAZE_0_I_BRAM_CTRL_UE_FAILING_REGISTERS,
		XPAR_MICROBLAZE_0_I_BRAM_CTRL_ECC_STATUS_REGISTERS,
		XPAR_MICROBLAZE_0_I_BRAM_CTRL_CE_COUNTER_WIDTH,
		XPAR_MICROBLAZE_0_I_BRAM_CTRL_ECC_ONOFF_REGISTER,
		XPAR_MICROBLAZE_0_I_BRAM_CTRL_ECC_ONOFF_RESET_VALUE,
		XPAR_MICROBLAZE_0_I_BRAM_CTRL_WRITE_ACCESS,
		XPAR_MICROBLAZE_0_I_BRAM_CTRL_BASEADDR,
		XPAR_MICROBLAZE_0_I_BRAM_CTRL_HIGHADDR,
		XPAR_MICROBLAZE_0_I_BRAM_CTRL_S_AXI_CTRL_BASEADDR,
		XPAR_MICROBLAZE_0_I_BRAM_CTRL_S_AXI_CTRL_HIGHADDR
	}
};


