Project Status (03/17/2014 - 10:16:26)
Project File: | system.xmp | Implementation State: | Programming File Generated
Module Name: | system | Errors: |
Product Version: | EDK 14.6 | Warnings: |

XPS Reports | [-]
Report Name | Generated | Errors | Warnings | Infos
Platgen Log File | H márc. 17 10:11:42 2014 | 0 | 3 Warnings (3 new) | 26 Infos (26 new)
Simgen Log File |  |  |  |
BitInit Log File |  |  |  |
System Log File | H márc. 17 10:16:25 2014 |  |  |

XPS Synthesis Summary (estimated values) | [-]
Report | Generated | Flip Flops Used | LUTs Used | BRAMS Used | Errors
system | H márc. 17 10:12:00 2014 | 4973 | 5751 | 28 | 0
system_logsys_axi_sp6_simpleio_0_wrapper | H márc. 17 10:11:21 2014 | 202 | 197 |  | 0
system_logsys_axi_spi_if_0_wrapper | H márc. 17 10:11:15 2014 | 177 | 267 |  | 0
system_logsys_axi_eth_if_0_wrapper | H márc. 17 10:11:07 2014 | 136 | 130 |  | 0
system_sdram_wrapper | H márc. 17 10:11:01 2014 | 222 | 477 |  | 0
system_axi4_0_wrapper | H márc. 17 10:10:53 2014 | 286 | 310 |  | 0
system_rs232_wrapper | H márc. 17 10:10:45 2014 | 85 | 106 |  | 0
system_axi4lite_0_wrapper | H márc. 17 10:10:38 2014 | 150 | 346 |  | 0
system_axi_timer_0_wrapper | H márc. 17 10:10:29 2014 | 222 | 321 |  | 0
system_clock_generator_0_wrapper | H márc. 17 10:10:21 2014 |  | 1 |  | 0
system_debug_module_wrapper | H márc. 17 10:10:17 2014 | 69 | 49 |  | 0
system_microblaze_0_wrapper | H márc. 17 10:10:11 2014 | 3263 | 3337 | 12 | 0
system_microblaze_0_bram_block_wrapper | H márc. 17 10:09:30 2014 |  |  | 16 | 0
system_microblaze_0_d_bram_ctrl_wrapper | H márc. 17 10:09:25 2014 | 2 | 6 |  | 0
system_microblaze_0_dlmb_wrapper | H márc. 17 10:09:20 2014 | 1 |  |  | 0
system_microblaze_0_i_bram_ctrl_wrapper | H márc. 17 10:09:15 2014 | 2 | 6 |  | 0
system_microblaze_0_ilmb_wrapper | H márc. 17 10:09:10 2014 | 1 |  |  | 0
system_microblaze_0_intc_wrapper | H márc. 17 10:09:06 2014 | 86 | 144 |  | 0
system_proc_sys_reset_0_wrapper | H márc. 17 10:08:58 2014 | 69 | 54 |  | 0

Device Utilization Summary (actual values) | [-]
Slice Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Registers | 3,904 | 11,440 | 34% |
Number used as Flip Flops | 3,893 |  |  |
Number used as Latches | 0 |  |  |
Number used as Latch-thrus | 0 |  |  |
Number used as AND/OR logics | 11 |  |  |
Number of Slice LUTs | 4,668 | 5,720 | 81% |
Number used as logic | 4,220 | 5,720 | 73% |
Number using O6 output only | 3,041 |  |  |
Number using O5 output only | 110 |  |  |
Number using O5 and O6 | 1,069 |  |  |
Number used as ROM | 0 |  |  |
Number used as Memory | 269 | 1,440 | 18% |
Number used as Dual Port RAM | 88 |  |  |
Number using O6 output only | 0 |  |  |
Number using O5 output only | 4 |  |  |
Number using O5 and O6 | 84 |  |  |
Number used as Single Port RAM | 7 |  |  |
Number using O6 output only | 0 |  |  |
Number using O5 output only | 1 |  |  |
Number using O5 and O6 | 6 |  |  |
Number used as Shift Register | 174 |  |  |
Number using O6 output only | 55 |  |  |
Number using O5 output only | 9 |  |  |
Number using O5 and O6 | 110 |  |  |
Number used exclusively as route-thrus | 179 |  |  |
Number with same-slice register load | 152 |  |  |
Number with same-slice carry load | 3 |  |  |
Number with other load | 24 |  |  |
Number of occupied Slices | 1,429 | 1,430 | 99% |
Number of MUXCYs used | 748 | 2,860 | 26% |
Number of LUT Flip Flop pairs used | 5,153 |  |  |
Number with an unused Flip Flop | 1,676 | 5,153 | 32% |
Number with an unused LUT | 485 | 5,153 | 9% |
Number of fully used LUT-FF pairs | 2,992 | 5,153 | 58% |
Number of unique control sets | 269 |  |  |
Number of slice register sites lost to control set restrictions | 1,078 | 11,440 | 9% |
Number of bonded IOBs | 86 | 102 | 84% |
Number of LOCed IOBs | 86 | 86 | 100% |
IOB Flip Flops | 155 |  |  |
Number of RAMB16BWERs | 28 | 32 | 87% |
Number of RAMB8BWERs | 0 | 64 | 0% |
Number of BUFIO2/BUFIO2_2CLKs | 1 | 32 | 3% |
Number used as BUFIO2s | 1 |  |  |
Number used as BUFIO2_2CLKs | 0 |  |  |
Number of BUFIO2FB/BUFIO2FB_2CLKs | 0 | 32 | 0% |
Number of BUFG/BUFGMUXs | 3 | 16 | 18% |
Number used as BUFGs | 3 |  |  |
Number used as BUFGMUX | 0 |  |  |
Number of DCM/DCM_CLKGENs | 0 | 4 | 0% |
Number of ILOGIC2/ISERDES2s | 44 | 200 | 22% |
Number used as ILOGIC2s | 44 |  |  |
Number used as ISERDES2s | 0 |  |  |
Number of IODELAY2/IODRP2/IODRP2_MCBs | 16 | 200 | 8% |
Number used as IODELAY2s | 16 |  |  |
Number used as IODRP2s | 0 |  |  |
Number used as IODRP2_MCBs | 0 |  |  |
Number of OLOGIC2/OSERDES2s | 74 | 200 | 37% |
Number used as OLOGIC2s | 74 |  |  |
Number used as OSERDES2s | 0 |  |  |
Number of BSCANs | 1 | 4 | 25% |
Number of BUFHs | 0 | 128 | 0% |
Number of BUFPLLs | 0 | 8 | 0% |
Number of BUFPLL_MCBs | 0 | 4 | 0% |
Number of DSP48A1s | 5 | 16 | 31% |
Number of ICAPs | 0 | 1 | 0% |
Number of MCBs | 0 | 2 | 0% |
Number of PCILOGICSEs | 0 | 2 | 0% |
Number of PLL_ADVs | 1 | 2 | 50% |
Number of PMVs | 0 | 1 | 0% |
Number of STARTUPs | 0 | 1 | 0% |
Number of SUSPEND_SYNCs | 0 | 1 | 0% |
Average Fanout of Non-Clock Nets | 4.06 |  |  |

Performance Summary | [-]
Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Translation Report | Current | H márc. 17 10:12:56 2014 | 0 | 6 Warnings (6 new) | 2 Infos (2 new)
Map Report | Current | H márc. 17 10:15:08 2014 |  |  |
Place and Route Report | Current | H márc. 17 10:15:50 2014 | 0 | 23 Warnings (23 new) | 2 Infos (2 new)
Post-PAR Static Timing Report | Current | H márc. 17 10:16:02 2014 | 0 | 0 | 4 Infos (4 new)
Bitgen Report | Current | H márc. 17 10:16:26 2014 | 0 | 21 Warnings (21 new) | 0

Secondary Reports | [-]
Report Name | Status | Generated

Date Generated: 03/17/2014 - 10:16:26