Project Status (01/11/2014 - 12:44:14)
Project File: | system.xmp | Implementation State: | Programming File Generated
Module Name: | system | Errors: |
Product Version: | EDK 14.7 | Warnings: |

XPS Reports | [-]
Report Name | Generated | Errors | Warnings | Infos
Platgen Log File | P jan. 10 23:15:49 2014 | 0 | 5 Warnings (0 new) | 34 Infos (0 new)
Simgen Log File |  |  |  |
BitInit Log File |  |  |  |
System Log File | Szo jan. 11 02:54:50 2014 |  |  |

XPS Synthesis Summary (estimated values) | [-]
Report | Generated | Flip Flops Used | LUTs Used | BRAMS Used | Errors
system | P jan. 10 23:16:04 2014 | 5011 | 5159 | 28 | 0
system_logsys_plb_sp6_simpleio_0_wrapper | P jan. 10 23:15:45 2014 | 282 | 209 |  | 0
system_sdram_wrapper | P jan. 10 23:15:39 2014 | 216 | 466 |  | 0
system_logsys_plb_spi_if_0_wrapper | P jan. 10 23:15:32 2014 | 249 | 280 |  | 0
system_logsys_plb_eth_if_0_wrapper | P jan. 10 23:15:24 2014 | 229 | 127 |  | 0
system_clock_generator_0_wrapper | P jan. 10 23:15:18 2014 |  | 1 |  | 0
system_xps_intc_0_wrapper | P jan. 10 23:13:41 2014 | 159 | 139 |  | 0
system_proc_sys_reset_0_wrapper | P jan. 10 23:13:35 2014 | 69 | 54 |  | 0
system_mdm_0_wrapper | P jan. 10 23:13:30 2014 | 69 | 49 |  | 0
system_rs232_wrapper | P jan. 10 23:13:20 2014 | 142 | 144 |  | 0
system_xps_timer_0_wrapper | P jan. 10 23:13:14 2014 | 363 | 336 |  | 0
system_lmb_bram_wrapper | P jan. 10 23:13:07 2014 |  |  | 16 | 0
system_ilmb_cntlr_wrapper | P jan. 10 23:13:02 2014 | 2 | 6 |  | 0
system_dlmb_cntlr_wrapper | P jan. 10 23:12:57 2014 | 2 | 6 |  | 0
system_dlmb_wrapper | P jan. 10 23:12:52 2014 | 1 |  |  | 0
system_ilmb_wrapper | P jan. 10 23:12:48 2014 | 1 |  |  | 0
system_mb_plb_wrapper | P jan. 10 23:12:44 2014 | 129 | 121 |  | 0
system_microblaze_0_wrapper | P jan. 10 23:12:37 2014 | 3098 | 3221 | 12 | 0

Device Utilization Summary (actual values) | [-]
Slice Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Registers | 3,997 | 11,440 | 34% |
Number used as Flip Flops | 3,988 |  |  |
Number used as Latches | 0 |  |  |
Number used as Latch-thrus | 0 |  |  |
Number used as AND/OR logics | 9 |  |  |
Number of Slice LUTs | 4,293 | 5,720 | 75% |
Number used as logic | 3,793 | 5,720 | 66% |
Number using O6 output only | 2,650 |  |  |
Number using O5 output only | 104 |  |  |
Number using O5 and O6 | 1,039 |  |  |
Number used as ROM | 0 |  |  |
Number used as Memory | 258 | 1,440 | 17% |
Number used as Dual Port RAM | 88 |  |  |
Number using O6 output only | 4 |  |  |
Number using O5 output only | 0 |  |  |
Number using O5 and O6 | 84 |  |  |
Number used as Single Port RAM | 7 |  |  |
Number using O6 output only | 0 |  |  |
Number using O5 output only | 1 |  |  |
Number using O5 and O6 | 6 |  |  |
Number used as Shift Register | 163 |  |  |
Number using O6 output only | 52 |  |  |
Number using O5 output only | 1 |  |  |
Number using O5 and O6 | 110 |  |  |
Number used exclusively as route-thrus | 242 |  |  |
Number with same-slice register load | 214 |  |  |
Number with same-slice carry load | 6 |  |  |
Number with other load | 22 |  |  |
Number of occupied Slices | 1,429 | 1,430 | 99% |
Number of MUXCYs used | 712 | 2,860 | 24% |
Number of LUT Flip Flop pairs used | 4,955 |  |  |
Number with an unused Flip Flop | 1,457 | 4,955 | 29% |
Number with an unused LUT | 662 | 4,955 | 13% |
Number of fully used LUT-FF pairs | 2,836 | 4,955 | 57% |
Number of unique control sets | 265 |  |  |
Number of slice register sites lost to control set restrictions | 1,066 | 11,440 | 9% |
Number of bonded IOBs | 86 | 102 | 84% |
Number of LOCed IOBs | 86 | 86 | 100% |
IOB Flip Flops | 155 |  |  |
Number of RAMB16BWERs | 28 | 32 | 87% |
Number of RAMB8BWERs | 0 | 64 | 0% |
Number of BUFIO2/BUFIO2_2CLKs | 1 | 32 | 3% |
Number used as BUFIO2s | 1 |  |  |
Number used as BUFIO2_2CLKs | 0 |  |  |
Number of BUFIO2FB/BUFIO2FB_2CLKs | 0 | 32 | 0% |
Number of BUFG/BUFGMUXs | 3 | 16 | 18% |
Number used as BUFGs | 3 |  |  |
Number used as BUFGMUX | 0 |  |  |
Number of DCM/DCM_CLKGENs | 0 | 4 | 0% |
Number of ILOGIC2/ISERDES2s | 44 | 200 | 22% |
Number used as ILOGIC2s | 44 |  |  |
Number used as ISERDES2s | 0 |  |  |
Number of IODELAY2/IODRP2/IODRP2_MCBs | 16 | 200 | 8% |
Number used as IODELAY2s | 16 |  |  |
Number used as IODRP2s | 0 |  |  |
Number used as IODRP2_MCBs | 0 |  |  |
Number of OLOGIC2/OSERDES2s | 74 | 200 | 37% |
Number used as OLOGIC2s | 74 |  |  |
Number used as OSERDES2s | 0 |  |  |
Number of BSCANs | 1 | 4 | 25% |
Number of BUFHs | 0 | 128 | 0% |
Number of BUFPLLs | 0 | 8 | 0% |
Number of BUFPLL_MCBs | 0 | 4 | 0% |
Number of DSP48A1s | 5 | 16 | 31% |
Number of ICAPs | 0 | 1 | 0% |
Number of MCBs | 0 | 2 | 0% |
Number of PCILOGICSEs | 0 | 2 | 0% |
Number of PLL_ADVs | 1 | 2 | 50% |
Number of PMVs | 0 | 1 | 0% |
Number of STARTUPs | 0 | 1 | 0% |
Number of SUSPEND_SYNCs | 0 | 1 | 0% |
Average Fanout of Non-Clock Nets | 3.83 |  |  |

Performance Summary | [-]
Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Translation Report | Current | P jan. 10 23:19:01 2014 | 0 | 42 Warnings (42 new) | 2 Infos (2 new)
Map Report | Current | P jan. 10 23:20:45 2014 |  |  |
Place and Route Report | Current | P jan. 10 23:21:24 2014 | 0 | 23 Warnings (23 new) | 0
Post-PAR Static Timing Report | Current | P jan. 10 23:21:35 2014 | 0 | 0 | 3 Infos (3 new)
Bitgen Report | Current | P jan. 10 23:21:56 2014 | 0 | 21 Warnings (21 new) | 0

Secondary Reports | [-]
Report Name | Status | Generated
WebTalk Report | Current | P jan. 10 23:21:57 2014
WebTalk Log File | Current | P jan. 10 23:22:05 2014

Date Generated: 01/11/2014 - 12:44:15